(1) Field of the invention
The present invention relates to parallel driven PWM (Pulse Width Modulation)-type power inverting units and, particularly, to a circuit and method for controlling an output current balance applicable to output current balancing of output currents derived from both or plural parallel driven PWM-type power inverting units so as to eliminate a deviation between output currents derived from both parallel driven power inverting units.
(2) Description of the background art
Semiconductor devices such as transistors, SCR, etc. are commonly used as switching elements of a main circuit of a single power inverter and/or converter. The inverter and converter generally constitute a power inverting unit from alternating currents to direct currents. In order to provide a high capacity for the whole power inverting unit, a plurality of power inverting units are driven in parallel to one another (simultaneously).
When the parallel drive for the power inverting units is carried out, output currents from the plural power inverting units become often unbalanced to each other due to variations in switching element characteristics internal of the respective power units and, in worst case, cross currents are generated between the respective units.
The term cross current generally means a circulation current flowing through respective windings of both electric equipments due to a difference in an induced electromotive force between both electric equipments in a case where both electric equipments are driven in parallel.
Main causes of generating such an output current unbalance as described above may be listed as follows: a difference in wiring impedance between both power inverting units; a difference in on voltages of the respective switching elements; a time difference of dead times added to prevent simultaneous on between upper and lower arms in the main circuits of the respective power inverting units; and a difference between storage times in the switching elements used in both power inverting units.
Output current unbalancing problem due to the difference in wiring impedance can be solved by rearranging the wiring between each element of the respective power inverting units to reduce in errors of the wiring impedances. In addition, the unbalancing due to the difference in dead times can be solved by digitalizing the whole circuitry in each power inverting unit.
The output current unbalancing problem due to the differences in the on voltages of the switching elements and their storage times can slightly be suppressed by selections of the excellent performance switching elements themselves. However, this method cannot cope with temperature variations between the individual switching elements.
FIG. 1 shows partial output circuits of one-phase main circuit of previously proposed parallel driven inverting units.
FIG. 2 shows situations how variations occur in switching times of transistors used as switching elements, particularly, how current errors due to the difference in storage times of the switching elements are generated in the case shown in FIG. 1 in which the output currents flow positively into an interphase reactor.
FIG. 3 shows situations how variations occur in switching times of transistors used as switching elements, particularly, how current errors due to the difference in storage times of the switching elements are generated in the case shown in FIG. 1 but in a case where the output currents I.sub.A and I.sub.B negatively flow out of the interphase reactor.
In both of FIGS. 2 and 3, on times and dead times are all the same for the described transistors shown in FIG. 1 and only the storage times T.sub.SUA, T.sub.SUB, T.sub.SXA, T.sub.SXA, and T.sub.SXB are changed according to their external circumstances.
These differences in storage times cause output voltages of V.sub.A and V.sub.B to produce an error voltage of V.sub.A-V.sub.B. In addition, the current unbalance between the output currents I.sub.A and I.sub.B is generated.
As shown in FIGS. 4 and 5, a current balance is achieved by a current feedback control method applied to the parallel driven power inverting units.
That is to say, in FIG. 4, in order to drive two inverters 1 and 2 in parallel, each of the two inverters having a current control system (ACR: Automatic Current Regulator) and a PWM inverting circuit (PWM), the same current command is issued to the respective current control amplifiers and the output current for each inverter 1, 2 is feedback controlled to the current command.
In the case of FIG. 5, an output of a deviation amplifier 4 which detects only an unbalanced component of the output currents is used to feedback control for an output of the current control amplifier (ACR) 3.
In the former method of FIG. 4, since no current command itself is present in an open loop control such as a V/F (voltage/frequency) drive type inverter, the output current balancing method cannot physically be realized any more.
In the latter method of FIG. 5, since a balance control circuit is inserted in a subsequent stage of each inverter, conventional various circuits can be applied thereto.
FIG. 6 shows a previously proposed current balance control circuit having a specific circuit construction applicable to the current balance circuit in the case of FIG. 5.
In FIG. 6, the previously proposed current balance control circuit includes a PWM control circuit having: a PWM command generator 5 which outputs an analog signal (sinusoidal wave); a PWM carrier oscillator 6 which outputs a triangular wave; and comparators 7, 8 which compare both levels of the output signals from the PWM command generator 5 and PWM carrier oscillator 6, respectively.
Gate signals V.sub.A, V.sub.B of the PWM waveforms which serve as outputs of the comparators 7 and 8 are input to the main circuits 9, and 10 including dead time generators and base drivers so as to provide PWM outputs PWM-A and PWM-B for the respective inverter main circuits 9, 10.
The outputs of both main circuits of inverters 9, 10 are supplied to an induction motor 12 which serves as a load via an interphase reactor 11.
To achieve the current balance, a difference in the output currents of the main circuits 9, 10 of the inverters 9, 10 is detected by means of the deviation amplifier 4, the deviation causing the output of the PWM command generator 5 to be increased or to be decreased and the increase or decrease being in conformity to polarity of the deviation.
FIG. 7 shows waveforms appearing on the current balance control circuit shown in FIG. 6.
If a difference exists between analog command voltages V.sub.a, V.sub.b of the PWM waveform outputs V.sub.A, V.sub.B from the comparators 7, 8 with respect to the output voltage V from the PWM command generator 5, i.e., the unbalance of the positive currents is present, the output of the deviation amplifier 4 causes the analog voltage V.sub.b to the comparator 8 to be increased and causes the analog voltage V.sub.a to the comparator 7 to be decreased. Together with decreasing a plusewidth of the output PWM-A of the inverter main circuit 9 (hatched portion of FIG. 7), the pulsewidth of the output PWM-B of the inverter main circuit 10 is increased as denoted by the hatch portion of FIG. 7. Consequently, the inverter output currents can be balanced.
However, in the previously proposed current balance method described above, the balance compensation is carried out in an analog system. The previously proposed current balance method cannot be applied to digitalized inverters nor converters in which a microcomputer is used in an essential part of control portion and self-contained PWM control ICs are used.
For example, an addition and/or subtraction of a balance compensated signals to and/or from the PWM commands cannot be carried out due to the presence of analog circuits in such inverters as those using the PWM control digital ICs. In addition, if the balance compensated signals are input into the internal of a CPU (Central Processing Unit) of the microcomputer via an A/D (Analog/Digital) converter, wasteful times are consumed to convert the analog signal to the corresponding digital signal and for the CPU to calculate and process the digitally processed operations, Consequently, such a method as described above cannot be reduced into practice in terms of their inherent responsive characteristics.